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ltc1863l/ltc1867l 1 1863l7lfa applicatio s u block diagra w features descriptio u industrial process control high speed data acquisition battery operated systems multiplexed data acquisition systems imaging systems sample rate: 175ksps 16-bit no missing codes and 3lsb max inl 8-channel multiplexer with: single ended or differential inputs and unipolar or bipolar conversion modes spi/microwire tm serial i/o 2.7v guaranteed supply voltage pin compatible with ltc1863/ltc1867 true differential inputs on-chip or external reference low power: 750 a at 175ksps, 300 a at 50ksps sleep mode automatic nap mode between conversions 16-pin narrow ssop package micropower, 3v, 12-/16-bit, 8-channel 175ksps adcs the ltc ? 1863l/ltc1867l are pin compatible, 8-channel 12-/16-bit a/d converters with serial i/o and an internal reference. the 8-channel input multiplexer can be configured for either single-ended or differential inputs and unipolar or bipolar conversions (or combinations thereof). the adcs convert 0v to 2.5v unipolar inputs or 1.25v bipolar inputs. the adcs typically draw only 750 a from a single 2.7v supply. the automatic nap and sleep modes benefit power sensitive applications. the ltc1867ls dc performance is outstanding with a 3lsb inl specification and 16-bit no missing codes over temperature. housed in a compact, narrow 16-pin ssop package, the ltc1863l/ltc1867l can be used in space-sensitive as well as low power applications. ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7/com 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 v dd gnd sdi sdo sck cs/conv v ref 1863l7l bd serial port analog input mux refcomp 9 internal 1.25v ref ltc1863l/ltc1867l 12-/16-bit 175ksps adc + C integral nonlinearity vs output code (ltc1867l) , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. output code 0 inl (lsb) 0 0.5 1.0 65536 1863l7l g01 C0.5 C1.0 C2.0 16384 32768 49152 C1.5 2.0 1.5 v dd = 2.7v f sample = 175ksps
ltc1863l/ltc1867l 2 1863l7lfa co verter characteristics u supply voltage (v dd ) ................................... C0.3v to 6v analog input voltage ch0-ch7/com (note 3) .......... C 0.3v to (v dd + 0.3v) v ref , refcomp (note 4)......... C 0.3v to (v dd + 0.3v) digital input voltage (sdi, sck, cs/conv) (note 4) .................................................C 0.3v to 10v digital output voltage (sdo) ....... C 0.3v to (v dd + 0.3v) power dissipation .............................................. 500mw operating temperature range ltc1863lc/ltc1867lc/ltc1867lac .... 0 c to 70 c ltc1863li/ltc1867li/ltc1867lai .. C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number t jmax = 110 c, ja = 95 c/w ltc1863lcgn ltc1863lign ltc1867lcgn ltc1867lign ltc1867lacgn ltc1867laign absolute axi u rati gs w ww u package/order i for atio uu w (notes 1, 2) the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 2.7v, external v ref = 1.25v (notes 5, 6) top view gn package 16-lead narrow plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7/com v dd gnd sdi sdo sck cs/conv v ref refcomp order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ ltc1863l ltc1867l ltc1867la parameter conditions min typ max min typ max min typ max units resolution 12 16 16 bits no missing codes 12 15 16 bits integral linearity error unipolar (note 7) 1 4 3 lsb bipolar 1 4 3 lsb differential linearity error 1 C2 C1 lsb transition noise 0.1 1.6 1.6 lsb rms offset error unipolar (note 8) 3 32 32 lsb bipolar 4 64 64 lsb offset error match unipolar 1 4 3 lsb bipolar 1 4 3 lsb offset error drift 0.5 0.5 0.5 ppm/ c gain error unipolar 6 96 64 lsb bipolar 6 96 64 lsb gain error match unipolar 1 4 3 lsb bipolar 1 4 3 lsb gain error tempco internal reference 20 20 20 ppm/ c external reference 3 3 3 ppm/ c power supply sensitivity v dd = 2.7v C 3.6v 1 3 3 lsb consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade for the 1867l is identified by a label on the shipping container. gn part marking* 1863l 1863li 1867l v dd = 3v, external v ref = 1.25v (note 5) dy a ic accuracy u w ltc1863l ltc1867l/ltc1867la symbol parameter conditions min typ max min typ max units snr signal-to-noise ratio 1khz input signal 73.1 83.7 db s/(n+d) signal-to-(noise + distortion) ratio 1khz input signal 73 83.1 db
ltc1863l/ltc1867l 3 1863l7lfa a alog i put u u i ter al refere ce characteristics uu u digital i puts a d digital outputs u u ltc1863l ltc1867l/ltc1867la symbol parameter conditions min typ max min typ max units thd total harmonic distortion 1khz input signal, up to 5th harmonic C91.8 C 92.3 db peak harmonic or spurious noise 1khz input signal C94.8 C 95.1 db channel-to-channel isolation 100khz input signal C100 C112 db full power bandwidth C3db point 1.25 1.25 mhz the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) (note 5) symbol parameter conditions min typ max units analog input range unipolar mode (note 9) 0 to 2.5 v bipolar mode 1.25 v c in analog input capacitance for ch0 to between conversions (sample mode) 32 pf ch7/com during conversions (hold mode) 4 pf t acq sample-and-hold acquisition time 2.01 1.68 s input leakage current on channels, chx = 0v or v dd 1 a parameter conditions min typ max units v ref output voltage i out = 0 1.235 1.25 1.265 v v ref output tempco i out = 0 20 ppm/ c v ref line regulation 2.7v v dd 3.6v 0.3 mv/v v ref output resistance ? i out ? 0.1ma 3 k ? refcomp output voltage i out = 0 2.5 v symbol parameter conditions min typ max units v ih high level input voltage v dd = 3.6v 1.9 v v il low level input voltage v dd = 2.7v 0.45 v i in digital input current v in = 0v to v dd 10 a c in digital input capacitance 2pf v oh high level output voltage (sdo) v dd = 2.7v, i o = C10 a 2.68 v v dd = 2.7v, i o = C200 a 2.3 2.65 v v ol low level output voltage (sdo) v dd = 2.7v, i o = 160 a 0.05 v v dd = 2.7v, i o = 1.6ma 0.15 0.4 v i source output source current sdo = 0v C9.7 ma i sink output sink current sdo = v dd 6ma hi-z output leakage cs/conv = high, sdo = 0v or v dd 10 a hi-z output capacitance cs/conv = high (note 10) 15 pf data format unipolar straight binary bipolar twos complement the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) ltc1863l/ltc1867l/ltc1867la ltc1863l/ltc1867l/ltc1867la ltc1863l/ltc1867l/ltc1867la v dd = 3v, external v ref = 1.25v (note 5) dy a ic accuracy u w
ltc1863l/ltc1867l 4 1863l7lfa symbol parameter conditions min typ max units v dd supply voltage (note 9) 2.7 3.6 v i dd supply current f sample = 175ksps, internal ref 0.75 1 ma nap mode 170 a sleep mode 0.2 3 a p diss power dissipation f sample = 175ksps 2 2.7 mw ti i g characteristics u w the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) symbol parameter conditions min typ max units f sample maximum sampling frequency 175 khz t conv conversion time 3.2 3.7 s t acq acquisition time 2.01 1.68 s f sck sck frequency 20 mhz t 1 cs/conv high time short cs/conv pulse mode 40 100 ns t 2 sdo valid after sck c l = 25pf (note 11) 22 47 ns t 3 sdo valid hold time after sck c l = 25pf 517 ns t 4 sdo valid after cs/conv c l = 25pf 20 40 ns t 5 sdi setup time before sck 15 C6 ns t 6 sdi hold time after sck 15 6 ns t 7 sleep mode wake-up time c refcomp = 10 f, c vref = 2.2 f80ms t 8 bus relinquish time after cs/conv c l = 25pf 30 50 ns note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to gnd (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma without latchup. note 4: when these pin voltages are taken below gnd, they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. these pins are not clamped to v dd . note 5: v dd = 2.7v, f sample = 175ksps and f sck = 20mhz at 25 c, t r = t f = 5ns and v in C = 1.25v for bipolar mode unless otherwise specified. note 6: linearity, offset and gain error specifications apply for both unipolar and bipolar modes. the inl and dnl are tested in bipolar mode. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: unipolar offset is the offset voltage measured from +1/2lsb when the output code flickers between 0000 0000 0000 0000 and 0000 0000 0000 0001 for ltc1867l and between 0000 0000 0000 and 0000 0000 0001 for ltc1863l. bipolar offset is the offset voltage measured from C1/2lsb when output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 for ltc1867l, and between 0000 0000 0000 and 1111 1111 1111 for ltc1863l. note 9: recommended operating conditions. the input range of 1.25v for bipolar mode is measured with respect to v in C = 1.25v. for unipolar mode, common mode input range is 0v to v dd for the positive input and 0v to 1.5v for the negative input. for bipolar mode, common mode input range is 0v to v dd for both positive and negative inputs. note 10: guaranteed by design, not subject to test. note 11: t 2 of 47ns maximum allows f sck up to 10mhz for rising capture with 50% duty cycle and f sck up to 20mhz for falling capture (with 3ns setup time for the receiving logic). power require e ts w u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) ltc1863l/ltc1867l/ltc1867la ltc1863l/ltc1867l/ltc1867la
ltc1863l/ltc1867l 5 1863l7lfa typical perfor a ce characteristics uw integral nonlinearity vs output code differential nonlinearity vs output code 4096 points fft plot (v dd = 2.7v, internal ref) 4096 points fft plot (v dd = 3v, refcomp = ext 3v) crosstalk vs input frequency signal-to-(noise + distortion) ratio vs input frequency power supply feedthrough vs ripple frequency (ltc1867l) supply current vs f sample (ltc1863l/ltc1867l) frequency (khz) 0 C60 C40 0 65.625 1863l7l g04 C80 C100 21.875 43.75 87.5 C120 C140 C20 amplitude (db) f sample = 175ksps f in = 1khz snr = 84.7db sinad = 83.5db thd = 90db f sample (ksps) 1 500 supply current ( a) 600 700 800 10 100 1000 1863l7l g09 400 300 200 100 v dd = 2.7v active channel input frequency (khz) C120 resulting amplitude on selected channel (db) C100 C90 C70 C60 0.1 10 100 1000 1863l7l g05 C140 1 C80 C110 C130 v dd = 3v f sample = 175ksps adjacent pair nonadjacent pair input frequency (khz) 1 20 amplitude (db) 40 60 100 10 100 1863l7l g06 80 30 50 90 70 v dd = 3v internal ref f sample = 175ksps snr sinad total harmonic distortion vs input frequency input frequency (khz) 1 C20 amplitude (db) C40 C60 C100 10 100 1863l7l g06 C80 C30 C50 C90 C70 v dd = 3v internal ref f sample = 175ksps thd sfdr ripple frequency (khz) 1 C60 power supply feedthrough (db) C40 C20 10 100 1000 1863l7l g08 C80 C70 C50 C30 C90 C100 v dd = 3v f sample = 175ksps v ripple = 10mv p-p output code 0 inl (lsb) 0 0.5 1.0 65536 1863l7l g01 C0.5 C1.0 C2.0 16384 32768 49152 C1.5 2.0 1.5 v dd = 2.7v f sample = 175ksps output code 0 dnl (lsb) 0 0.5 1.0 65536 1863l7l g02 C0.5 C1.0 C2.0 16384 32768 49152 C1.5 2.0 1.5 v dd = 2.7v f sample = 175ksps frequency (khz) 0 C60 C40 0 65.625 1863l7l g03 C80 C100 21.875 43.75 87.5 C120 C140 C20 amplitude (db) f sample = 175ksps f in = 1khz snr = 82.9db sinad = 81.4db thd = 86.8db
ltc1863l/ltc1867l 6 1863l7lfa typical perfor a ce characteristics uw supply current vs supply voltage supply current vs temperature (ltc1863l/ltc1867l) differential nonlinearity vs output code (ltc1863l) integral nonlinearity vs output code (ltc1863l) histogram for 4096 conversions (ltc1867l) refcomp vs load current supply voltage (v) 2.7 600 supply current ( a) 700 800 900 1000 1200 3 3.3 1963l7l g10 3.6 1100 f sample = 175ksps temperature ( c) C50 500 supply current ( a) 750 1000 1250 1500 C25 0 25 50 1863l7l g11 75 100 3.6v dd 3.3v dd 2.7v dd 3v dd f sample = 175ksps internal ref code 20 7 0 counts 200 400 600 800 1200 22 24 26 28 1863l7l g12 30 21 23 25 27 29 31 1000 58 465 1044 895 830 261 23 9 1 170 333 v dd = 2.7v internal ref load current (ma) 0 2.495 2.500 2.510 1.5 1863l7l g13 2.490 2.485 0.5 1 2 2.480 2.475 2.505 refcomp (v) v dd = 2.7v offset drift (ltc1867l) vs temperature temperature ( c) C50 C10 unipolar offset (lsb) C5 0 5 10 C25 0 25 50 1863l7l g14 75 100 bipolar mode unipolar mode v dd = 2.7v f sample = 175ksps ext v ref = 1.25v gain error drift (ltc1867l) vs temperature temperature ( c) C50 C15 unipolar offset (lsb) C10 C5 0 5 15 C25 02550 1863l7l g15 75 100 10 v dd = 2.7v f sample = 175ksps ext v ref = 1.25v unipolar/bipolar code 0 inl (lsb) 0 0.50 4096 1863l7l g16 C0.50 C1.00 1024 2048 3072 512 1536 2560 3584 1.00 C0.25 0.25 C0.75 0.75 code 0 dnl (lsb) 0 0.50 4096 1863l7l g17 C0.50 C1.00 1024 2048 3072 512 1536 2560 3584 1.00 C0.25 0.25 C0.75 0.75
ltc1863l/ltc1867l 7 1863l7lfa uu u pi fu ctio s cho-ch7/com (pins 1-8): analog input pins. analog inputs must be free of noise with respect to gnd. ch7/ com can be either a separate channel or the common minus input for the other channels. unused channels should be tied to ground. refcomp (pin 9): reference buffer output pin. bypass to gnd with 10 f tantalum capacitor in parallel with 0.1 f ceramic capacitor (2.5v nominal). to overdrive refcomp, tie v ref to gnd. v ref (pin 10): 1.25v reference output. this pin can also be used as an external reference buffer input for improved accuracy and drift. bypass to gnd with 2.2 f tantalum capacitor in parallel with 0.1 f ceramic capacitor. cs/conv (pin 11): this input provides the dual function of initiating conversions on the adc and also frames the serial data transfer. sck (pin 12): shift clock. this clock synchronizes the serial data transfer. sdo (pin 13): digital data output. the a/d conversion result is shifted out of this output. straight binary format for unipolar mode and twos complement format for bipolar mode. sdi (pin 14): digital data input pin. the a/d configuration word is shifted into this input. gnd (pin 15): analog and digital gnd. v dd (pin 16): analog and digital power supply. bypass to gnd with 10 f tantalum capacitor in parallel with 0.1 f ceramic capacitor. test circuits uu u typical co ectio diagra u u ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7/com v dd gnd sdi sdo sck cs/conv v ref refcomp ltc1863l/ ltc1867l C + + digital i/o 2.7v to 3.6v 10 f 2.5v 10 f 2.2 f 1.25v 1.25v differential inputs 2.5v single-ended input 1863l7l tcd 3k (a) hi-z to v oh and v ol to v oh c l 3k 2.7v sdo sdo (b) hi-z to v ol and v oh to v ol c l 1863l7l tc01 3k (a) v oh to hi-z c l 3k 2.7v sdo sdo (b) v ol to hi-z c l 1863l7l tc02 load circuits for access timing load circuits for output float delay
ltc1863l/ltc1867l 8 1863l7lfa ti i g diagra s w u w t 5 (sdi setup time before sck ), t 6 (sdi hold time after sck ) 50% 50% t 3 0.45v t 7 (sleep mode wake-up time) t 7 sck cs/conv t 8 (bus relinquish time) t 8 cs/conv sdo 1.9v t 4 (sdo valid after cs/conv ) t 4 cs/conv sdo 1.9v 0.45v 0.45v t 6 1.9v 0.45v t 5 sck sdi 1.9v 1.9v 0.45v 1.9v 0.45v sdo 1863l7l td sleep bit (slp = 0) read-in 10% 90% hi-z hi-z t 1 (for short pulse mode) t 2 (sdo valid after sck ), t 3 (sdo valid hold time after sck ) t 1 cs/conv t 2 sck 50% 50% overview the ltc1863l/ltc1867l are complete, low power, multi- plexed adcs. they consist of a 12-/16-bit, 175ksps capaci- tive successive approximation a/d converter, a precision internal reference, a configurable 8-channel analog input multiplexer (mux) and a serial port for data transfer. conversions are started by a rising edge on the cs/conv input. once a conversion cycle has begun, it cannot be restarted. between conversions, the adcs receive an input word for channel selection and output the conversion result, and the analog input is acquired in preparation for the next conversion. in the acquire phase, a minimum time of 2.01 s will provide enough time for the sample-and- hold capacitors to acquire the analog signal. during the conversion, the internal differential 16-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). the input is sucessively compared with the binary weighted charges supplied by the differential capacitive dac. bit decisions are made by a low power, differential comparator that rejects common mode noise. at the end of a conversion, the dac output balances the analog input. the sar content (a 12-/16-bit data word) that represents the analog input is loaded into the 12-/16-bit output latches. applicatio s i for atio wu uu
ltc1863l/ltc1867l 9 1863l7lfa applicatio s i for atio wu uu examples of multiplexer options ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7/com gnd ( C ) 8 single-ended + + + + + + + 4 differential + ( C ) + ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7/com ( C ) 7 single-ended to ch7/com + + + + + + + + ( C ) + ( C ) + ( C ) C ( + ) C ( + ) C ( + ) C ( + ) gnd ( C ) combinations of differential and single-ended + + + + + + C C { { { { { { 1863l7l ai01 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7/com ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7/com analog input multiplexer the analog input multiplexer is controlled by a 7-bit input data word. the input data word is defined as follows: sd os s1 s0 com uni slp sd = single/differential bit os = odd/sign bit s1 = address select bit 1 s0 = address select bit 0 com = ch7/com configuration bit uni = unipolar/bipolar bit slp = sleep mode bit applicatio s i for atio wu uu tables 1 and 2 show the configurations when com = 0, and com = 1. table 1. channel configuration (when com = 0, ch7/com pin is used as ch7) channel configuration sd os s1 s0 com ? 00000 ch0 ch1 00010 ch2 ch3 00100 ch4 ch5 00110 ch6 ch7 01000 ch1 ch0 01010 ch3 ch2 01100 ch5 ch4 01110 ch7 ch6 10000 ch0 gnd 10010 ch2 gnd 10100 ch4 gnd 10110 ch6 gnd 11000 ch1 gnd 11010 ch3 gnd 11100 ch5 gnd 11110 ch7 gnd table 2. channel configuration (when com = 1, ch7/com pin is used as common) channel configuration sd os s1 s0 com "+" "? 10001 ch0 ch7/com 10011 ch2 ch7/com 10101 ch4 ch7/com 10111 ch6 ch7/com 11001 ch1 ch7/com 11011 ch3 ch7/com 11101 ch5 ch7/com changing the mux assignment ?n the fly ch7/com (unused) ch7/com ( C ) 1st conversion 2nd conversion + C + C + C + + { { { { ch2 ch3 ch4 ch5 ch2 ch3 ch4 ch5 1863l7l ai02
ltc1863l/ltc1867l 10 1863l7lfa driving the analog inputs the analog inputs of the ltc1863l/ltc1867l are easy to drive. each of the analog inputs can be used as a single- ended input relative to the gnd pin (ch0-gnd, ch1-gnd, etc) or in pairs (ch0 and ch1, ch2 and ch3, ch4 and ch5, ch6 and ch7) for differential inputs. in addition, ch7 can act as a com pin for both single-ended and differential modes if the com bit in the input word is high. regardless of the mux configuration, the + and C inputs are sampled at the same instant. any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. the inputs draw only one small current spike while charg- ing the sample-and-hold capacitors during the acquire mode. in conversion mode, the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low then the ltc1863l/ltc1867l inputs can be driven directly. more acquisition time should be allowed for a higher impedance source. the following list is a summary of the op amps that are suitable for driving the ltc1863l/ltc1867l. more de- tailed information is available in the linear technology data books or linear technology website. lt ? 1468: 90mhz, 22v/ s 16-bit accurate amplifier lt1469: dual lt1468 lt1490a/lt1491a: dual/quad micropower amplifiers, 50 a/amplifier max, 500 v offset, common mode range extends 44v above v C independent of v + , 3v, 5v and 15v supplies. lt1568: very low noise, active rc filter building block, cutoff frequency up to 10mhz, 2.7v to 5v supplies. lt1638/lt1639: dual/quad 1.2mhz, 0.4v/ s amplifiers, 230 a per amplifier, 3v, 5v and 15v supplies. lt1881/lt1882: dual and quad, 200pa bias current, rail- to-rail output op amps, up to 15v supplies. ltc1992-2: gain of 2 fully differential input/output am- plifier/driver, 2.5mv offset, c load stable, 2.7v to 5v supplies. lt1995: 30mhz, 1000v/ s gain selectable amplifier, pin configurable as a difference amplifier, inverting and noninverting amplifier, 2.5v to 15v supplies. ltc6912: dual programmable gain amplifiers with spi serial interface, 2mv offset, 2.7v to 5v supplies. ltc6915: zero drift, instrumentation amplifier with spi programmable gain, 125db cmrr, 0.1% gain accuracy, 10 v offset. input filtering the noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the ltc1863l/ltc1867l noise and distortion. noisy in- put circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is sufficient for many applications. for instance, figure 1 shows a 50 ? source resistor and a 2000pf capacitor to ground on the input will limit the input bandwidth to 1.6mhz. the source impedance has to be kept low to avoid gain error and degradation in the ac performance. the capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the adc input from sampling glitch sensitive circuitry. high quality capacitors and resistors should be applicatio s i for atio wu uu 1863l7l f01a ch0 gnd ltc1863l/ ltc1867l refcomp 2000pf 10 f 50 ? analog input 1000pf 1863l7l f01b ch0 ch1 ltc1863l/ ltc1867l refcomp 1000pf 1000pf 10 f 50 ? 50 ? differential analog inputs figure 1a. optional rc input filtering for single-ended input figure 1b. optional rc input filtering for differential inputs
ltc1863l/ltc1867l 11 1863l7lfa used since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linear- ity. carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resis- tors are much less susceptible to both problems. dc performance one way of measuring the transition noise associated with a high resolution adc is to use a technique where a dc signal is applied to the input of the adc and the resulting output codes are collected over a large number of conver- sions. for example, in figure 2 the distribution of output codes is shown for a dc input that had been digitized 4096 times. the distribution is gaussian and the rms code transition noise is about 1.6lsb. applicatio s i for atio wu uu figure 2. ltc1867l histogram for 4096 conversions figure 3a. ltc1867l nonaveraged 4096 point fft plot with 2.7v supply components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 3a shows a typical sinad of 81.4db with a 175khz sampling rate and a 1khz input. higher sinad can be obtained with a 3v supply. for example, when an exter- nal 3v is applied to refcomp (tie v ref to gnd), a sinad of 83.5db can be achieved as shown in figure 3b. figure 3b. ltc1867l nonaveraged 4096 point fft plot with 3v supply code 20 7 0 counts 200 400 600 800 1200 22 24 26 28 1863l7l g12 30 21 23 25 27 29 31 1000 58 465 1044 895 830 261 23 9 1 170 333 v dd = 2.7v internal ref dynamic performance fft (fast fourier transform) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algo- rithm, the adcs spectral content can be examined for frequencies outside the fundamental. signal-to-noise ratio the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency frequency (khz) 0 C60 C40 0 65.625 1863l7l g03 C80 C100 21.875 43.75 87.5 C120 C140 C20 amplitude (db) f sample = 175ksps f in = 1khz snr = 82.9db sinad = 81.4db thd = 86.8db frequency (khz) 0 C60 C40 0 65.625 1863l7l f03b C80 C100 21.875 43.75 87.5 C120 C140 C20 amplitude (db) f sample = 175ksps f in = 1khz snr = 84.7db sinad = 83.5db thd = 90db refcomp = ext 3v total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency
ltc1863l/ltc1867l 12 1863l7lfa compensation pin, refcomp, must be bypassed with a 10 f ceramic or tantalum in parallel with a 0.1 f ceramic for best noise performance. digital interface the ltc1863l and ltc1867l have a very simple digital interface that is enabled by the control input, cs/conv. a logic rising edge applied to the cs/conv input will initiate a conversion. after the conversion, taking cs/conv low will enable the serial port and the adc will present digital data in twos complement format in bipolar mode or straight binary format in unipolar mode, through the sck/ sdo serial port. internal clock the internal clock is factory trimmed to achieve a typical conversion time of 3.2 s and a maximum conversion time, 3.7 s, over the full operating temperature range. the typical acquisition time is 1.68 s, and a throughput sam- pling rate of 175ksps is tested and guaranteed. automatic nap mode the ltc1863l and ltc1867l go into automatic nap mode when cs/conv is held high after the conversion is com- plete. with a typical operating current of 750 a and auto- matic 170 a nap mode between conversions, the power dissipation drops with reduced sample rate. the adc only keeps the v ref and refcomp voltages active when the part is in the automatic nap mode. the slower the sample rate allows the power dissipation to be lower (see figure 5). r2 r3 reference amp 10 f 2.2 f refcomp gnd v ref r1 3k 10 9 15 1.25v 2.5v ltc1863l/ltc1867l 1863l7l f04a bandgap reference 10 0.1 f 10 f 1863l7l f04b lt1790a-1.25 v out v in 3v v ref ltc1863l/ ltc1867l gnd refcomp 15 9 + 2.2 f band between dc and half the sampling frequency. thd is expressed as: thd vvv v v n = ++ + 20 2 2 3 2 4 22 1 log ... where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. internal reference t he ltc1863l and ltc1867l have an on-chip, tempera- ture compensated, curvature corrected, bandgap refer- ence that is factory trimmed to 1.25v. it is internally connected to a reference amplifier and is available at v ref (pin 10). a 3k resistor is in series with the output so that it can be easily overdriven by an external reference if better drift and/or accuracy are required as shown in figure 4. the reference amplifier gains the v ref voltage by 2x to 2.5v at refcomp (pin 9). this reference amplifier figure 4b. using the lt1790a-1.25 as an external reference figure 4a. ltc1867l reference circuit applicatio s i for atio wu uu figure 5. supply current vs f sample f sample (ksps) 1 500 supply current ( a) 600 700 800 10 100 1000 1863l7l g09 400 300 200 100 v dd = 2.7v
ltc1863l/ltc1867l 13 1863l7lfa if the cs/conv returns low during a bit decision, it can create a small error. for best performance ensure that the cs/conv returns low either within 100ns after the conver- sion starts (i.e. before the first bit decision) or after the conversion ends. if cs/conv is low when the conversion ends, the msb bit will appear on sdo at the end of the conversion and the adc will remain powered up. sleep mode if the slp = 1 is selected in the input word, the adc will enter sleep mode and draw only leakage current (pro- vided that all the digital inputs stay at gnd or v dd ). after release from the sleep mode, the adc needs 80ms to wake up (charge the 2.2 f/10 f bypass capacitors on v ref /refcomp pins). board layout and bypassing to obtain the best performance, a printed circuit board with a ground plane is required. layout for the printed circuit board should ensure digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital signal alongside an analog signal. all analog inputs should be screened by gnd. v ref , refcomp and v dd should be bypassed to this ground plane as close to the pin as possible; the low impedance of applicatio s i for atio wu uu the common return for these bypass capacitors is essen- tial to the low noise operation of the adc. the width for these tracks should be as wide as possible. timing and control conversion start is controlled by the cs/conv digital input. the rising edge transition of the cs/conv will start a conversion. once initiated, it cannot be restarted until the conversion is complete. figures 6 and 7 show the timing diagrams for two types of cs/conv pulses. example 1 (figure 6) shows the ltc1863l/ltc1867l operating in automatic nap mode with cs/conv signal staying high after the conversion. automatic nap mode provides power reduction at reduced sample rate. the adcs can also operate with the cs/conv signal returning low before the conversion ends. in this mode (example 2, figure 7), the adcs remain powered up. the digital output, sdo, will go high immediately after the conversion is complete if the analog inputs are above half scale in unipolar mode or below half scale in bipolar mode. this is a way to measure the conversion time of the a/d converter. figures 8 and 9 are the transfer characteristics for the bipolar and unipolar mode. s0 sd 0s s1 com uni slp d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1/f sck cs/conv sck sdi sdo (ltc1863l) hi-z d12 d15 d14 d13 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hi-z 12345678910111213141516 1867 f06 don't care don't care not needed for ltc1863l t conv nap mode sdo (ltc1867l) msb msb figure 6. example 1, cs/conv starts a conversion and remains high until next data transfer. with cs/conv remaining high after the conversion, automatic nap modes provides power reduction at reduced sample rate
ltc1863l/ltc1867l 14 1863l7lfa applicatio s i for atio wu u u figure 7. example 2, cs/conv starts a conversion with short active high pulse. with cs/conv returning low before the conversion, the adc remains powered up. input voltage (v) output code 1863l7l f09 111...111 111...110 100...001 100...000 000...000 000...001 011...110 011...111 fs C 1lsb 0v unipolar zero fs = 2.5v 1lsb = fs/2 n 1lsb (ltc1863l) = 610 v 1lsb (ltc1867l) = 38.1 v figure 8. ltc1863l/ltc1867l bipolar transfer characteristics (two? complement) figure 9. ltc1863l/ltc1867l unipolar transfer characteristics (straight binary) s0 sd 0s s1 com uni slp msb = d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cs/conv sck sdi sdo (ltc1867l) hi-z 12345678910111213141516 t conv d12 msb = d15 d14 d13 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hi-z 1863l7l f07 t conv don't care don't care not needed for ltc1863l t acq sdo (ltc1863l) input voltage (v) 0v output code (twos complement) C1 lsb 1863l7l f08 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fs/2 C 1lsb Cfs/2 fs = 2.5v 1lsb = fs/2 n 1lsb (ltc1863l) = 610 v 1lsb (ltc1867l) = 38.1 v
ltc1863l/ltc1867l 15 1863l7lfa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio u gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 15 14 13 .189 C .196* (4.801 C 4.978) 12 11 10 9 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .007 C .0098 (0.178 C 0.249) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
ltc1863l/ltc1867l 16 1863l7lfa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt/lt 0605 rev a ? printed in usa related parts part number description comments ltc1417 14-bit, 400ksps serial adc 20mw, unipolar or bipolar, internal reference, ssop-16 package lt1468/lt1469 single/dual 90mhz, 22v/ s, 16-bit accurate op amps low input offset: 75 v/125 v ltc1609 16-bit, 200ksps serial adc 65mw, configurable bipolar and unipolar input ranges, 5v supply lt1790 micropower low dropout reference 60 a supply current, 10ppm/ c, sot-23 package lt1790a-1.25 micropower precision series reference bandgap, 60 a max supply current, 10ppm/ c, sot-23 package ltc1850/ltc1851 10-bit/12-bit, 8-channel, 1.25msps adc parallel output, programmable mux and sequencer, 5v supply ltc1852/ltc1853 10-bit/12-bit, 8-channel, 400ksps adc parallel output, programmable mux and sequencer, 3v or 5v supply ltc1860/ltc1861 12-bit, 1-/2-channel 250ksps adc in msop 850 a at 250ksps, 2 a at 1ksps, so-8 and msop packages ltc1860l/ltc1861l 3v, 12-bit, 1-/2-channel 150ksps adc 450 a at 150ksps, 10 a at 1ksps, so-8 and msop packages ltc1863/ltc1867 12-/16-bit, 8-channel 200ksps adc 5v supply, pin compatible with ltc1863l/ltc1867l ltc1864/ltc1865 16-bit, 1-/2-channel 250ksps adc in msop 850 a at 250ksps, 2 a at 1ksps, so-8 and msop packages ltc1864l/ltc1865l 3v, 16-bit, 1-/2-channel 150ksps adc in msop 450 a at 150ksps, 10 a at 1ksps, so-8 and msop packages

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